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| 6-BIT 2:1 MUX-LATCH SY10E155 SY100E155 FINAL FEATURES s s s s s s s 750ps max. LEN to output Extended 100E VEE range of -4.2V to -5.5V 700ps max. D to output Single-ended outputs Asynchronous Master Reset Dual latch-enables Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E155 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. The two external latch-enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the six latches. When both LEN1 and LEN2 are at a logic LOW, the latches are transparent, thus presenting the data from the multiplexers at the output pins. If either LEN1 or LEN2 (or both) are at a logic HIGH, the outputs are latched. The multiplexer operation is controlled by the SEL (Select) signal which selects one of the two bits of input data at each mux to be passed through. The MR (Master Reset) signal operates asynchronously to take all outputs to a logic LOW. BLOCK DIAGRAM D0a MUX D0b D1a MUX D1b D2a MUX D2b D3a MUX D3b D4a MUX D4b D5a MUX D5b SEL LEN1 LEN2 MR SEL SEL SEL SEL SEL SEL D E NR D E NR D E NR D E NR D E NR D E NR Q Q5 Q Q4 Q Q3 Q Q2 Q Q1 Q Q0 PIN CONFIGURATION D3a NC VCCO D5a D4b 25 24 23 22 21 20 19 D5b LEN1 LEN2 VEE MR SEL D0b D4a D3b 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 Q5 Q4 VCC Q3 Q2 VCCO Q1 PLCC TOP VIEW J28-1 16 15 14 13 12 D2b VCCO D0b D1a D1b D2a PIN NAMES Pin D0a-D5a D0b-D5b SEL LEN1, LEN2 MR Q0-Q5 VCCO Function Input Data a Input Data b Data Select Input Latch Enables Master Reset Outputs VCC to Output Q0 Rev.: C Amendment: /1 1 Issue Date: February, 1998 Micrel SY10E155 SY100E155 TRUTH TABLES SEL H L Data a b LEN1 L H X LEN2 L X H Latch Transparent Latched Latched DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 85 85 102 102 -- -- 85 85 102 102 -- -- 85 98 102 117 Min. -- TA = +25C Max. 150 TA = +85C Min. Typ. -- -- Max. 150 Unit A mA Condition -- -- Typ. Max. Min. Typ. -- 150 -- -- AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output D SEL LEN MR Set-up Time D SEL Hold Time D SEL Reset Recovery Time Minimum Pulse Width, MR Within-Device Skew Rise/Fall Time 20% to 80% Min. 325 475 350 450 300 500 300 0 800 400 -- 300 TA = +25C Max. 700 925 750 850 -- -- -- -- -- -- -- 800 TA = +85C Min. Typ. 325 475 350 450 300 500 300 0 800 400 -- 300 500 675 500 600 100 250 -100 -250 650 -- 75 450 Max. 700 925 750 850 ps 100 250 -100 -250 650 -- 75 450 -- -- -- -- -- -- -- 800 300 500 300 0 800 400 -- 300 100 250 -100 -250 650 -- 75 450 -- -- ps -- -- -- -- -- 800 ps ps ps ps -- -- 1 -- -- -- Unit ps 500 675 500 600 700 925 750 850 325 475 350 450 500 675 500 600 Condition -- Typ. Max. Min. Typ. tS tH tRR tPW tskew tr tf NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code SY10E155JC SY10E155JCTR SY100E155JC SY100E155JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial 2 Micrel SY10E155 SY100E155 28 LEAD PLCC (J28-1) Rev. 03 3 Micrel SY10E155 SY100E155 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
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